Various methods for electrically connecting bare die integrated circuits to printed circuit substrates to form multi-chip modules are well known in the art. Among all the types of multi-chip modules, the technique of flip chip with solder bumps has the most promise with regard to electrical performance, size reduction and price. A flip chip is an unpackaged integrated circuit chip in which the bonding pads have solder bumps formed on them. Solder bumps are approximately hemispherically shaped solidified solder attached to the bonding pads and are typically of a tin-lead composition. The unpackaged chip does not have a plastic shell or metallic leads common to most integrated circuit packages. The active side of the flip chip contains the active devices and bonding pads and has a passivation layer that protects the chip's active components from environmental contaminants. The solder bumps of the flip chip then are positioned in registering contact with the substrate circuit conductive contact areas.
When heated, the bumps reflow and the chip floats on the solder. Depending on the bump volume and spacing, molten solder surface tension and chip weight, this uncontrolled reflow can lead to solder joints of uncontrolled shape and height. The result is that the integrated circuit, or flip chip, will have an unpredictable spacing between it and the substrate it is attached to. Nonuniform operation and shorting out of circuit components can occur when reflow from adjacent bumps run together. Furthermore, fatigue failures of the solder joints can result from stresses caused by differential thermal expansion and contraction between the silicon chip and the organic substrate.
Epoxy underfill is often required for reliability of the flip chip interconnect when attached to substrates like standard printed circuit boards which have thermal coefficients of expansion much different than silicon. The epoxy adds structural strength to the mechanical connection between the flip chip and the substrate, while absorbing most of the stresses that would have otherwise been absorbed by the solder joints as a result of temperature cycling. The epoxy is placed under the flip chip through the use of an underfill process. This process is carried out by flowing the epoxy slowly under the chip. It is then driven the rest of the way under the chip by capillary action. Too narrow of a spacing between the chip and substrate will slow down or stop the underfill rate. Controlling the chip spacing, or standoff, is required for a repeatable underfill flow process. Enhancing or increasing the die standoff provides for a reasonable underfill flow process cycle time. Complete coverage of the underfill material is required for reliability. Complete underfill can be assured by increasing and controlling the chip standoff.
A characteristic of flip chips is that they are physically smaller than their packaged counterparts. As a result, adequate heat dissipation can be a problem. Hence there may be a requirement for heat sink to be physically placed on the chips to enhanced reliability. The placement of heat sinks requires that the physical spacing of the flip chip be well controlled. The attachment of a single heat sink for an array of flip chips also requires uniform chip height and parallel spacing.
A prior solution to controlling the spacing between a flip chip and the substrate is the Controlled Collapse Chip Connection (C4) technique. This technology utilizes bumps by evaporation electro-plating or other means with a composition of 95-97% Pb and Sn. The melting temperature of the bumps exceeds 320.degree. C. In order to use C4 with organic substrates such as FR-4, eutectic solder is added to form the interconnect at a much lower temperature (&lt;183.degree. C.). The disadvantage of this approach is that the total cost for evaporation of the bumps and the addition of eutectic solder on the substrate is high. This approach utilizes a plated copper stud over the metal pads on the substrate which are printed with eutectic solder paste. The hope is that both the copper studs and the lead-rich solder bumps wet the eutectic solder while it melts maintaining a "uniform" spacing of the near eutectic solder between the studs and the leadrich bumps. Control of the "uniform" spacing is limited to a great extent by the tolerance of the paste printed.
U.S. Pat. No. 5,056,215 shows pillars for spacing an integrated circuit above a substrate. The pillars are manufactured by printing layers of dielectric thick film on the substrate. This process is limited because printing the thick film layers does not allow much control of the shape of the pillars. The repeatability of dimension from one pillar to the next is generally poor because screen printing is nonuniform and it is very difficult to manufacture multi-layer pillars due to layer to layer registration errors. All of these characteristics make it difficult to predict and control the spacing dimensions between the bare chip integrated circuit and the substrate.
Another prior solution is to try and constrain the flow of solder, or wicking, on the substrate conductive pads. This is attempted by placing a solder mask or dam over portions of the conductive pads to constrain the solder flow. Solder mask is coated over the conductive traces on a substrate and resists the flow of molten solder. This method enhances the chip standoff by constraining the wicking of the solder onto the substrate by defining the bumps with precisely placed solder mask. The disadvantage of this solution is the difficulty and the cost associated with meeting the required solder mask registration tolerance.
It is desirable to provide controlled standoff for a flip chip integrated circuit to be assembled over a circuit containing substrate with minimal extra material and process steps.